1. Field of the Invention
The invention relates to a method of a multi-step high density plasma (HDP) chemical vapor deposition (CVD), and more particularly to a method of filling a gap between conductive structures in a semiconductor device with dielectric material.
2. Description of the Related Art
In a semiconductor device, multilevel conductive wiring and other conductors are normally isolated by inter-metal dielectric (IMD) layers. As the dimension of device shrinks, the aspect ratio of the gap between conductive layers increases. The gap with a higher aspect ratio is more difficult to fill. On the other hand, as the distance between conductive layers and other conductors becomes shorter, the capacitance increases, so that the operating speed is limited. To achieve a higher efficiency with the shrinking dimension of devices, the dielectric layer between conductive layers are required to have characteristics such as being filled within the gap evenly and uniformly, preventing the water flow, and minimizing the capacitance between conductive layers by using a low dielectric constant material.
Thus, it is important to deposit a high quality, interstice-free dielectric layer to fill a gap with a high aspect ratio. The dielectric layer is formed, for example, by CVD which is performed by introducing the precursor to the deposition surface, and after reaction, the material is deposited on the surface. Different kinds of CVD processes are in use, such as atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), and plasma enhanced CVD (PECVD). To obtain high quality oxide by APCVD and LPCVD, a high deposition temperature such as about 650.degree. C. to 850.degree. C. is required. However, for some conductive material, for example, aluminum, such a high deposition temperature causes voids within oxide. Structures like voids absorb water, and thus, are not a proper IMD layer. By PECVD, plasma provides extra energy for reacting gases, and therefore, the deposition is performed at a low temperature, for example, about 400.degree. C. or lower.
In a conventional method of forming a dielectric layer between conductive wiring, an interlayer is formed by PECVD using silane or tetra-ethyl-ortho-silicate (TEOS) as precursor. An accompanying spin-on-glass (SOG) layer is formed on the conductive wiring and to fill the gap which is between the conductive wiring. However, due to the characteristics of absorbing water and the formation of interstices, SOG layer cannot fill the gap completely. This phenomenon is even more obvious as the devices become smaller. Thus, a method for filling the gap with a high quality dielectric material is developed.
In addition, in a device with a smaller dimension, the conventional CVD cannot fill a gap with a higher aspect ratio completely. For example, using PECVD, interstices between conductive wiring are sealed by the deposited material. In the subsequent process, the interstices are open and contaminated. Therefore, the conductive wiring or the contact are damaged, and the device is degraded.
FIGS. 1A and 1B show a method of filling a gap by a conventional PECVD process. In FIG. 1A, an oxide layer 10 is formed on a substrate 12 by PECVD with TEOS as a precursor. On an upper part of the side wall of the conductive wiring 14, an overhang 15 is formed. As the deposition continues, an interstice 16 is sealed as shown in FIG. 2. The interstice 16 is formed as a seam along the conductive wiring lengthwisely. The seam is near the end of the conductive wiring, or is restricted in the bending part of the conductive wiring. In the subsequent process, the interstice 16 is very likely to be uncovered, so that chemical for polishing or the by-product for etching is trapped by the interstice. Removing the trapped material within the interstice is very difficult. Thus, the yield of the subsequent process is degraded.